[FM-India] Open Project Position at Formal Methods Group IIT Kharagpur

[Madhavan Mukund]

OPEN PROECT POSITION IN THE FORMAL METHODS RESEARCH GROUP, IIT KHARAGPUR

PROJECT TITLE: Formal Methods for Verification of Power Management in Mixed-Signal Designs
PROJECT SPONSOR: Intel Corp.
ELIGIBILITY AND PAY:  Please see advertisement in IIT Kharagpur web page under jobs

Integrated circuits use sophisticated power management strategies to
switch off idle parts of the chip, bring them up when needed and
control the voltage and clock frequency at which they operate. The
components may include analog circuits such as PLLs and LDOs, and
therefore the power management logic must consider the latencies of
such circuits to ensure correct operation of the integrated
circuit. In practice, the task of verifying that the power management
logic correctly does all these is very challenging, given that
simulation of such circuits with analog behaviors is very time
consuming. This project aims at using a new genre of formal techniques
for statically analysing the power management logic and proving its
correctness under specified assumptions of the analog components. This
project offers interesting research challenges and the opportunity to
work with scientists from the leading chip design company of the
world.
 
We primarily develop software tools for verification ? therefore
proficiency in programming is essential.
 
This project is inter-disciplinary in nature, and students afraid of
venturing into domains outside their own need not apply. Students in
Electrical / Electronics / Instrumentation Engg with willingness to
learn formal language and automata theory are welcome. Also students
in Computer Science and Engg with willingness to learn about
integrated circuits (including analog) are welcome.
 
The Formal Verification Research Group, IIT Kharagpur is recognized as
one of the best groups in this area in the world. The group works on a
wide variety of application domains, including verification of digital
and analog integrated circuits, verification of real time control
systems, software verification, verification of smart electrical grids
and verification of railway signalling and train control
systems. Formal verification techniques combine formal languages and
logic, automata theory, and symbolic decision procedures like SAT and
SMT. The group develops tools and technology for formal verification
and applies them to real world problems in collaboration with a wide
spectrum of industries including Intel, IBM, Synopsys, General Motors,
SRC, Indian Railways, Hindustan Aeronautics Ltd., and Freescale
Semiconductors. For more information, you may look up Prof Dasgupta?s
web page: http://cse.iitkgp.ac.in/~pallab
 
We will also have other open positions in the next two/three months
(in other projects). If you are interested to be considered for this
as well as the upcoming positions, please submit your profile in the
following link: http://goo.gl/forms/wF3iOacxFv

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Dr. Pallab Dasgupta
FNAE, FASc, FIETE,
Associate Dean (Sponsored Research & Industrial Consultancy), and
Professor, Department of Computer Science & Engineering,
Indian Institute of Technology Kharagpur.
Ph: +91-3222-282047, 283470 (off) 283471 (res)
Web: http://cse.iitkgp.ac.in/~pallab
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