[FM-India] FMIndia Digest, Vol 88, Issue 7

Yogananda Jeppu yvjeppu at gmail.com
Sat Jul 30 18:48:53 IST 2016

 Exploring Design Verifier – 4 uploaded
Natasha Jeppu and I have uploaded the 4th set of models to explore Simulink
Design Verifier and formal methods. These models can be used to teach
engineers this interesting subject of Formal Methods. We revisit the
Therac-25 problem. We have an aerospace standard 3 sensor voter logic and
the up/down counter. There is a set of NuSMV files also included which are
similar to the Simulink models. This can be used for comparison. The voter
check presents a framework which the students can use to evaluate different
voter logic using formal methods.


Yogananda Jeppu

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